Видео

Thank you for the appreciation. I have a lot more content available on RUclips for free, which you can access through my channel or see in a more convenient layout on the EnICS Labs website enicslabs.com/education/ I'd love to hear more feedback and I hope to find time to create more content over the summer.

Great to hear! Please give me feedback on my other videos and I'm open to suggestions for more material (though, who knows when I'll find time to record more :)

EDA stands for Electronic Design Automation. This is the general name of the programs used to design chips. We also call them CAD (computer-aided design) tools, but CAD is used in other fields, whereas EDA is usually used for hardware design utilities. I suggest watching my other courses to learn all about this field. You can find my material at enicslabs.com/education/

You are most welcome

All of the slides are available on the EnICS Labs website. The webpage for this course is at: enicslabs.com/academic-courses/dvd-english/

@@AdiTeman thanks for your reply but I cant find the direct link to download it, can you please provide it?

@@thangdaoviet419 No problem. There is a button on the right panel of each lecture that says "Lecture X Slides". For this specific lecture, the link is: www.dropbox.com/scl/fi/d5sqn83htkyifkbed7nfu/Lecture-3-Synthesis-Part-1.pdf?rlkey=e0jfxerycb03brp3feq3q265t&dl=0

@@AdiTeman thank you very much, have a nice day ^^

Thank you! That's what makes me motivated to provide more material (hopefully, I will have time to make some more videos later this year).

You are so welcome. That is what they are there for! Hopefully I will find time to prepare more videos later this year. I have a long queue of lectures waiting to be recorded - I just have to find the free time to get around to it.

Well, I don't know if just watching the videos is enough, but it is a good start!

Yes, you are right. There is an "extra" dx there. Thank you for pointing this out (it "magically" disappeared on the next slide ;)

@@AdiTeman Thank you for the clarification, Professor. I really enjoyed the lecture and appreciate your guidance on this point.

Thanks!

Hi, Sorry that I haven't provided it as of yet. I may be updating the course recordings soon (a lot has changed since 2020...) and maybe then I could add some labs.

Hi. Tough question. These things mostly run on Linux and aren't too friendly for home computers. But you can start by buying a starter FPGA and programming it. The FPGAs come with a tool suite that runs on Windows and you can learn a ton from it (and FPGA design is a very popular and required skill on its own). Try starter kits from Xilinx or Altera.

Hi Haziq, Indeed, this is a really bad naming convention, but I didn't invent it. Maybe I should have changed it, because it's so upside down, but I kept what was in a reference that I based it on. You can see in the bottom figure that the usage of DIN/DOUT is the same (pay attention that the PAD is connecting outside the chip, while the ports are connected to the chip core). I can try to give a makeshift explanation, but really, it is going to be a bad one, because if I were to design these I/Os, I would label the pins in the opposite way. Here it goes - "we are looking at the I/O from the perspective of the other chip, so its outputs are connected to DOUT and its inputs to DIN. Where the other chip is receiving is the RX I/O and where it is transmitting is the TX one". So after we got that horrible explanation out of the way, I will say that these things just depend on whatever the vendor who developed the circuit decided to call it. So you have to read the manual (good luck ;) and adhere to it.

@@AdiTeman well the explanation isn't that horrible. And by not changing it, you saved the students from future confusion. Thanks!

בקישור יש כפתור ליד כל הרצאה עם קישור למצגת.

Hi, Actually, your question made me go look this up again and make sure I didn't make a mistake in the lecture and it also showed me something that I'm not sure how deeply I thought about it before. Luckily, there is no mistake in the lecture (as far as I can tell), but maybe I should have given the example a bit differently to make it more clear. What we want to do is fill a number into a register that doesn't fit in the immediate field of addi (so >4096). What we have to do is break it down into two numbers. The first, we multiply by 4096 and then we add the second to it. The number, therefore, that gets stored in the example is 456x4096+789. This can be a bit complicated due to sign extension and twos complement numbers. Therefore, we usually wouldn't write this sequence by hand, but rather use the compiler pseudoinstruction "li" (load immediate). This is, assuming that you actually are hand writing your assembly code, rather than doing what most people do, which is using a high level language ;). But for the purpose of understanding this, if I would have done lui 0x456 addi 789, then I would have gotten 0x456789 in the register (because a <<12 operation is 3 hexa positions).

Just another point, There is a great discussion about this here: stackoverflow.com/questions/50742420/risc-v-build-32-bit-constants-with-lui-and-addi

@@AdiTeman Thanks sir. Sorry for not mentioning the time stamp while asking the question.

Wow, that is such a great question. It is something I have been teaching for years as an option, but seemed to never have thought about what it's good for! Your question made me look it up. I will say that clock trees are a bigger subject than I discuss in this lecture - much bigger. Every chip has new "surprises" in the clock tree that make you use these different definitions, and every time I have run into one, I say "I'll use that as an example in a lecture on CTS", but by the time it becomes relevant (usually, this is in the middle of a tapeout or other stressful times ;), I totally forget the scenario and why we needed these weird commands... Anyway, back to your question, I found an answer. The general high-level reason is that there can be cases where a net is both on a clock path and a data path. In such a case, you want to buffer the clock part of the net, but not the data part of the net, so you would put "exclude" on the data pins. That is a great explanation, right? Well, the obvious question is "why the heck would a clock net be a data net as well???". And the answer is not too obvious. One answer could be that you may have some observation circuitry on the clock and you treat this as data. But one of the user manuals shows a more common case that actually makes sense and that is the case of a clock divider. A clock divider is just a bunch of flops, where the output of one drives the clock signal of the other with a toggled input. In this case, we have the Q pin of the flop driving a clock net and so it needs to be handled by CTS. Until now, all is good - we want these to be buffered and such. So this is not the case of mixing clock and data. HOWEVER, we perform scan insertion (which I didn't cover in this course), where all flops are connected in a shift register configuration (scan chain) for testing. In this case, the clock net emanating from the Q pin of the divider flop goes to the CK pin of the other divider flop, but also goes to the SI pin of the next flop in the scan chain. This IS a data path and shouldn't be treated as a clock net. So the SI pin should be regarded an EXCLUDE pin. (note, this may be handled inherently by the CTS engine). Thanks for pointing this out so I learned something new.

Hi Haziq, Your question is legitimate, because I can say that I have been confused by this more than once (don't tell anyone 😂). But actually, it's almost irrelevant. The reason is that we are building an estimator that is trying to somehow quantify the wirelength, so we can define a cost function and optimize it. It is very clear that our estimator is far from accurate - it just needs to represent something that is better or worse than something else, so we can change it and see if that helps. So counting the distance (|x1-x2|) or the number of blocks that the wire occupies (which comes out |x1-x2|+1) is essentially the same for the purpose we are using it. In addition to that, as you will see in the following parts of the lecture, we are actually using other estimators more predominantly (such as the quadratic wirelength estimator). But the point is the same - we are trying to put a number that represents how good or bad our solution is for comparison to a different solution. You could look at it as a rating system that gives you 1-5 stars or a grade of 1-10 - as long as the better option has a higher rating, it doesn't really matter what the scale is.

@@AdiTeman Thanks. I have completed the following parts of the lecture and got your point. Thank you for taking your time out and explaining.

@@haziqiqbalhussain Great

Thanks!

Hi, I don't think there's a problem. The "base" and "beginning" that I refer to are the same thing. Basically, it's the opposite of the stack pointer that points to the top of the stack. The frame pointer points to the bottom so we can return to where it started.

@@AdiTeman oh I see, thank you for replying

Glad to hear that!

Thank you!

Haha, Great catch! This slide (and video) has been around for quite some time and no one ever pointed that out. This is not an error, per se, since it's just an X (and 4'bx is basically the same as 1'bx) and the simulator and synthesizer would (hopefully) disregard this, but it was for sure unintentional in the slide. Thanks for finding this. I will pin the errata!

Hi, I think you just went beyond my pay grade :). I'm far from being an expert - and for sure when it comes to deep down things that affect analog simulations - that's out of my expertise. There are many gurus out there, but I've had the pleasure to meet two of them - Andrew Beckett of Cadence (he answers many questions on online Cadence forums and is amazingly knowledgeable) and Prof. Andrei Vladimirescu, one of the designers of SPICE (and author of "The SPICE Book"). Andrei is a good friend and would probably be happy to answer your question if you reached out to him (...and bonus points if you told him that I sent you ;).

Hi Lam, Luckily, the algorithms are deeply implemented into the tools, so we don't have to do anything ourselves in terms of implementing them ;)

Great to know that my lectures are reaching other disciplines. I'd also love to hear if there are any other thermal engineers watching these.

Hi, Yes, these can be cases for multiplexers on the clock tree. There are actually many cases where you would multiplex several clocks onto the same clock tree. Just as an example that is commonly found on SoCs: We usually provide two clocks: (1) An external reference (from a crystal) with a low frequency (usually less than 100MHz and sometimes much lower) (2) An internally generated clock from a PLL or other clock generator. When we boot the system, the generated clock is not available. It takes time for the PLL to "lock". Additionally, we want a backup in case the PLL doesn't work properly or something like that. So we drive both clocks into a Mux, boot with the external clock, and transfer to the internal clock once it is stable.

Hi, Thanks for the question. Some things we - experienced engineers - take for granted, since we're used to seeing them so often and we may not explain them (though I do vaguely remember explaining this in one of my lectures somewhere). The clock is very deterministic. Every clock period, it goes up once and down once and it does this repeatedly at a constant rate. Therefore, this is how we draw the clock signal. On the other hand, we don't know what the data is in a general case. It could be '1', could be '0', could stay constant and could toggle. Therefore, we draw it in that "changing" or "unknown" kind of way. It is supposed to represent "all cases" where we must take into account that any level can be there and where the X's are, it may be changing (it will be stable where the lines are straight).

You are welcome!

Hi, So I think this is covered in Lecture 3 (Synthesis - Part 1). Specifically, you can find the video about Liberty timing models here: ruclips.net/video/-NgWsQJCGls/видео.html I don't go into great detail about CCS models (they're actually very complicated), but I explain where they come from and such. Wire load models (WLM) are something a bit different and I cover them in this lecture, as well. They basically are just a (really poor) estimation of the RC load of a net based on the fanout.

Thanks

Hi, Sorry, but I don't know of any freely available courses on layout design. I'm not saying that there aren't any of these - I just am not aware of them. I am pretty sure that the leading EDA companies (e.g., Cadence, Synopsys, Siemens-EDA) provide such training and these are often free to academic participants. In addition, I get emails from KalTech (kaltech.co.il/ic-training/) with offers for their layout courses, but I have never taken one of them, so I cannot recommend them.

Hi, I'm not sure what you are commenting. I would like to point out that this short presentation is for digital-on-top integration. In other words, the flow is run in a digital place and route tool, such as Cadence Innovus or Synopsys Fusion. The point of the presentation is to discuss how to prepare a custom-designed block for integration in a digital flow. This is as opposed to analog-on-top, which is preparing the entire design in a transistor-level tool, such as Cadence Virtuoso. Here, the custom block will be designed in such a tool, but the overall tapeout will be prepared in the digital tool.

Thanks!

Hi. I'm not sure I understand the question exactly, but I'll try to answer. If you mean what to set as a default input transition - this is a good point. We want to model the input transition, but we don't know what is connected to the input and how. Therefore, the calculation will not be accurate. This is a limitation that cannot be overcome, but the point here is to get a "good estimate". In general, digital delay modeling is NOT ACCURATE (as opposed to SPICE), but provides a tradeoff between run-time and accuracy. So we are trying to get a number that is "good enough", while it is clear that this is not 100% right. In this case, we have two options - 1) provide a number that characterizes the process. This is very inaccurate and has nothing to do with CCS or the different gates. It's just some number that could be a reasonable transition so the delay of the next gate falls within the timing tables. 2) provide a typical gate from the library that may be connected to the input. In this case, the .lib (including CCS) of the gate is used for the delay calculation. This is not the gate that is actually connected, but is typical of the technology/library and therefore is a good estimate. In any case, these are just estimations. Not accurate. But better than assuming something that is not based on anything...

Thank you!

Thank you so much!

Yes, indeed, in these slides, ps is picoseconds

Hi Atul, Good observation. Indeed, it would seem that I broke one of the "unbreakable rules". But, as I like to tell the students in my courses, everything I describe as a "ground truth" actually has cases (sometimes very frequent cases), where it doesn't hold. This is a bit of that. When I defined the "law" of "do not put logic on the clock", I probably mentioned something like "unless you really know what you are doing". In this slide, I describe clock gating for low power design. The assign statement here is directly describing clock gating logic. In other words, "we really know what we are doing". In fact, there are many reasons to put logic on the clock, but as a beginning RTL designer, you do not want to do them. As an advanced RTL designer, you would be expected to understand the implications of doing this, and in 95% of the cases, you would understand that you're not supposed to do it. But there is still that 5%, where you understand really well why you want to put logic on the clock and they it will be correct. Regarding this specific case - you will probably never do this exactly. A single flip flop will not be clock gated. You would usually use enable logic (like the first example) and if there are several flops sharing the enable condition, the synthesizer will automatically insert an ICG. An assign, such as in this example, would usually be used on a global clock gating signal. But even then, usually you would instantiate a specific standard cell from the library and not use a synthesized assign.

Thank you!

Hi, Yes, that is an accurate observation. The immediate (constant) is encoded in the instruction, so it does not need to be fetched from the regfile and only one register needs to be read out. That said, this doesn't really "help" us from a hardware perspective. Since there are 2R1W operations, we need to support this capability, so there is no (straightforward) advantage of an addi operation over an R2R operation.

Hi, I'm not sure what you are asking - is it something from the slides I showed in my lecture or is this a question from something you have run into at your work? If it is from the slides, I probably got the image from something I found on the internet and can't vouch for the exact example. If it is something from "real life" then I can try and guess the following explanation. There is no 100% accurate standard or way to make library files and therefore you get different things from different vendors (and different products). Most of the time (yes, for almost every library or IP you get) there are things that don't exactly "fit" and you often need to "fidget" with them. This usually doesn't make it to the level of the design engineer, but is taken care of by the CAD team that makes sure that the entire flow works with the tools the company uses and the processes they are using. But believe me - there is a lot of adaptation of LEFs and LIBs from what you get from the foundry/vendor. With that, I can tell you that extra information is not detrimental; so you have OBS on an active layer - it's not going to do anything bad, just make the LEF file a few KB bigger. In a certain techfile, possibly the router could (strangely...) consider such a layer as a routing layer and then the LEF would need to add the diffusion as an obstruction. But this is not the standard way things are done, and it could lead to other not so nice consequences. But that may be the reason you see this...